In order to test RAM macros, e.g., SRAM directory macros, by means of Array Built In Self Test (ABIST), the data from the array is usually compared to expected data. To accomplish this, the ABIST requires additional circuitry. This additional circuitry is either embedded in the SRAM or provided in surrounding logic.
Directory macro's are microprocessor cache components that are used to determine if a particular address is currently held in the main cache RAM. Typically, a directory RAM holds a portion of the addresses stored in the main cache RAM. A portion of the full address is used to retrieve and latch an entry from the RAM. Another portion of the address (“tag”) is then compared against the latched entry from the RAM. If the tag matches the entry retrieved from the RAM, the cache is said to have found a “hit”.
Typically, the logic to accomplish this utilizes RAM output to generate a “hit” signal. A set of bits from the RAM are compared bit by bit with the corresponding tag bits using an XOR gate. The output of any XOR is a “1” if the corresponding RAM bit and tag bit are mismatched, that is, the tag bit and the RAM bit are not equal to each other. If, however, none of the XOR gates generate a mismatch, that is, all of the RAM bits are equal to the corresponding tag bits, then the output of a second stage NOR gate will be a “1”, meaning that the cache found a hit. The speed at which the cache can operate is directly affected by how long it takes for this compare structure to evaluate the inputs. This, in turn, depends upon the length of the logic path.
A clear need exists to reduce the length and complexity of the logic path, and thereby reduce the time required for the cache to operate.
There is also a clear need to reduce the circuit overhead of the directory compare and logic function and the ABIST error detection function.